The invention relates generally to chip packaging and, more particularly, to structures and methods for improving the ability to visualize alignment marks on an underfill-covered chip.
A chip may be mounted on a packaging substrate to create a chip package. Typically, solder balls or bumps on the component are placed in registration with pads on the packaging substrate and the solder bumps may be subsequently reflowed to create solder joints that join the packaging substrate and chip. The solder joints provide electrical and mechanical interconnections between the packaging substrate and chip, but also create a gap between the packaging substrate and chip.
Filling the open space between solder joints with an underfill material improves the reliability of the electrical and mechanical interconnections, and protects the fragile back-end-of-line (BEOL) chip structure. The presence of the underfill material also discourages moisture-based failure mechanisms potentially causing electrical shorting and component failure and blocks other contaminants from entering the space between the chip and the packaging substrate. The underfill material makes the interconnections fatigue and creep resistant and also permits the package to withstand shock loads from handling, temperature cycling and drop testing with either static or dynamic loads.
A wafer-level underfill (WLUF) process may be used to preapply the underfill material before the chip is joined with a packaging substrate. In an over-bump applied resin (OBAR) process, a filled resin is applied over the bumps of a wafer and dried. The wafer is diced into coated chips, which are individually aligned and joined to a packaging substrate resulting in an underfilled flip chip package.
When bonding a chip to its packaging substrate, the chip and packaging substrate may be aligned relative to each other using alignment marks on the chip and fiducial marks or alignment marks on the substrate. However, the filler content of a pre-applied underfill may render the underfill opaque. When the underfill is pre-applied on the chip, the alignment between the bumps on the chip and the pads on the packaging substrate may be hindered due to the opacity of the filled resin, which may obscure the ability to visualize the alignment marks and even the bumps on the chip.
Structures and methods are needed that improve the ability to visualize alignment marks on an underfill-covered chip.